With the advent of computers a need arose for the computer to communicate with peripherals such as memory, RAM's, PROM's, I/O peripherals, timers, interrupt controllers, etc. In order to control the access by the computer to the peripheral it was necessary to activate a fixed connection between the computer and the peripheral using intervening discrete logic. This was the common control mechanism for accessing peripherals until the advent of microprocessors. As IC's became common in computers, the discrete logic functions needed for accessing peripherals was moved from discrete logic to PROM's, then PLA's and PAL's which provide general programmable logic capability which was programmed for the discrete logic functions but because of the limited number of inputs were unable to provide sufficient decoding capability. As the number of inputs increase, the size of a PROM able to handle the decoding task increases exponentially thus rendering PROMs impractical. For instance, when 11 inputs are needed, a 2K word PROM was needed and each fuse required specific programming. Since a chip controller function ordinarily requires only about 10% of the available logic in a 2K PROM, PLA, or PAL, the remainder of the device is wasted.
For a PLA or PROM, up to 4,000 fuses, or other memory cells are included and the normal application would involve the programming of only up to about 300 memory elements with the remainder being excessive. However, it is necessary to render many of the remainder of the memory elements inoperative in order to prevent erroneous operation of the device. Additionally, due to the general nature of a PAL, it is necessary in some instances to establish an output function tailored to the chip select function requiring the programming of up to 300 memory elements. Of the remaining memory elements in the general purpose programmable logic devices, it is typically necessary to use only 10% of the memory to implement the chip select function. Thus, a substantial portion of the available logic goes unused.
An example of a current chip select implementation for a microprocessor is shown in FIG. 1 where a CPU which may be for example, an 80C86 microprocessor, will provide as an output (input to the chip select decode circuitry) address, data and control signals. These signals are received by 74HC373 latches which demultiplex the address and control information from the multiplexed bus to provide the address information to programmable inversion devices, shown here as 7 position DIP switches which in conjunction with the inverters 74HC04 establishes proper polarity of the address inputs. The address information is logically AND'ed with control signals to perform the appropriate chip select. This logic function is performed by the dual 2 to 4 line decoder. An AND function is provided for the purpose of reducing the number of lines provided to the line decoder. The output from the line decoder selects the peripheral device which the CPU intends to access.
In operation, the time required from the CPU's issuance of the command signal until the chip select decoder circuitry implements the command can be as high as 220 ns as specified in the data sheets for the above part types. Additionally, the power consumption of this CMOS implementation could typically be about 50-75 mw.
In situations where speed and reliability are more important, an alternative approach is illustrated in FIG. 2 utilizing commercially available bipolar logic devices. The address/data signals provided to the multiplexed bus by the CPU are received by the address latch 74ALS373 which strips off the address information from the multiplexed data bus and passes the address information to the Programmable Logic Device, shown as a 12L10. Control signals are also provided to the 12L10. The Programmable Logic Device is programmed to provide, as its output, a decoded chip select signal. This arrangement would typically require up to 125 ma (625 mw) and can provide access to the peripheral within 64 ns after the CPU's issuance of the command signal.
Activation of a peripheral device generally involves the provision of a first logic level to a device select input of the peripheral device. Deactivation of the peripheral device occurs whenever a second logic level signal is provided to its device select input. Upon activation, the peripheral device receives the data portion of the multiplexed signal on the multiplexed bus which data controls the operations of the peripheral.
The various approaches to implementing a chip select function are not uniformly acceptable due to either too slow an access time as with the embodiment of FIG. 1 or too great a power requirement as in the embodiment of FIG. 2. Additionally, the plurality of individual chips required to implement these approaches increases the risk of defective soldering of the chips to the circuit board, defective packaging, or defective board performance. Thus, if the the desired functions could be performed with increased speed, reduced power and on a single chip, the drawbacks associated with the existing alternatives could be overcome.
For purposes of demonstrating the inefficiencies associated with the use of existing approaches, the implementation of a chip select function utilizing a 12L10 is described. This approach is currently believed to be among the best available alternatives for a product designer. A 12L10 includes approximately 500 fuses only about 200 of which need to be programmed to perform a chip select decoder function. Thus, about 300 fuses are wasted in this example. The cost, in terms of final manufacturing yield, and costs associated with the extra circuit size required to provide an extra 300 fuses, could be avoided if an optimized programmable chip select decoder could be provided. Additionally, in the programming of a 12L10 for a chip select decoder function, it is necessary to program a significantly greater number of fuses than are actually used in the chip select decoder operation. This is required in order to insure that the unused fuses do not result in undesired operation. Thus, these extra fuses are rendered inactive by positively programming them out of the system. Thus, if a more efficient circuit architecture were provided, the programming of an excessive number of fuses could be avoided.